1. Field of the Invention
The present invention relates to a process for compensating a failure in a semiconductor device such as a microcomputer with a memory, and in particular, to a device for compensating a failure in a memory.
This application is based on Japanese Patent Application No. Hei 10-359798, the contents of which are incorporated herein by reference.
2. Description of the Related Art
Semiconductor devices such as microcomputers and DSPs (digital signal processors), in general, include memories such as RAMs and ROMs. As fine manufacturing technology has developed in recent years, integration of semiconductor devices has progressed remarkably, increasing the storage capacities of the memories built in the semiconductor devices.
As fine manufacturing technology has progressed, defects have tended to occur due to dust produced in the manufacturing process, and therefore the yield may be decreased. Particularly, because a mass storage memory includes a number of integrated memory cells, failed bits may frequently occur. Fine manufacturing processes may have a greater effect on the yield of memory cells than the yield of logic circuit portions. The failed bits in microcomputers with mass storage memory must be compensated.
Conventional general mass storage memories include a redundancy circuit which compensates the failed bits. This redundancy circuit includes spare columns and rows in the memory cell array, programs the failed address in a fuse circuit in advance, and selects the specified spare column or row when the address from external devices coincides with the failed address.
The disadvantage of conventional redundancy circuits is that they increase the manufacturing costs. Specifically, because the redundancy circuit is built in the memory, the number of elements and the scale of the circuitry of the memory are increased, resulting in an increased area for the memory. Further, an additional process is required to form the fuse elements in the fuse circuit. Moreover, a test process for specifying the address of failed bits, and a process for cutting the fuse are required. As the result, the costs of compensating the failure are increased. To store the failed address in the fuse circuit, the fuse elements must be trimmed by laser, which may cause damages on the surface of the chip, degrading the quality of the device.
Another problem of conventional redundancy circuits is that the compensation of failures is inefficient. Specifically, because the redundancy circuit substitutes the failed bits for the spare columns or rows, the failure over the entire column or row can be efficiently compensated. The efficiency of the compensation, however, may become poor when compensating a small number of failed bits or dispersed failed bits, that is, the conventional redundancy circuit cannot sufficiently cope with occurrences of various failed bits. When compensating a small number of failed bits, the ratio of the failed bits to the bits in the spare columns or rows becomes comparatively high, reducing the efficiency in the use of the spare bits (redundancy bits). Moreover, because the conventional redundancy circuit is intended to compensate all bits, the compensation of the failure is not completed unless all bits are substituted, even when a failed bit exists in an address area which is not actually used.
It is therefore an object of the present invention to provide a semiconductor device and a method which can efficiently compensate various failures without increasing the costs.
In one aspect of the present invention, the semiconductor device with a memory, comprises: a failure diagnostic device for diagnosing the memory to detect a failed address; and a failed bit compensation device for compensating a failed bit in the memory which is specified by the failed address, based on the diagnostic result by the failure diagnostic device.
According to the semiconductor device of the present invention, the failure diagnostic device diagnoses the built-in memory to detect the address of the failed bit in the memory. The failed bit compensation device compensates the failed bit. Thus, the present invention performs the self-diagnostic process for the memory, and compensates the failed bit, eliminating the failure compensation step from the manufacturing process. Because the failed bits specified by the failed address are individually compensated, the present invention can cope with various failures efficiently.
The failure diagnostic device diagnoses the memory within the address area for specified data (e.g., application program) to be stored in the memory. The address area in which data is not stored is excluded from the target of the diagnostic process, and the load of the failure diagnostic process can be decreased.
The failure diagnostic device diagnoses the memory using specified data to be stored in the memory.
Even when a failure exists, the failure is not detected as long as it does not hinder specified data from being stored. The target is limited to the minimum range in the memory required to store the specified data, thus minimizing the diagnostic process.
The failure diagnostic device diagnoses the memory outside the address area for. specified data to be stored in the memory, and detects a normal (defect-free) address, and the failed bit compensation device substitutes the failed address for the normal address.
The failed address is substituted for the normal spare address, that is, the failed bit is substituted for the normal bit in the free storage area in the memory. Therefore, the efficiency in the use of the bits in the memory is improved, and the scale of circuitry for the compensation of the failure is reduced.
The failed bit compensation device comprises: a register group for substituting the failed bit; a failed address storage device for storing the failed address detected by the failure diagnostic device; an address coincidence detection device for detecting the coincidence between the failed address stored in the failed address storage device and the address sent to the memory; and a selector for selecting one of the memory and the register group to a data bus, based on the detection result by the address coincidence detection device.
The address coincidence detection device compares the address sent to the memory with the failed address stored in the failed address storage device, and detects the coincidence. Based on this detection, one of the memory and the register group is selected and is connected to the data bus. When the failed address is accessed, the failed address is substituted for the register group, to thereby compensate the failure in the memory. Further, the failed bit compensation device replaces the failed bit, specified by the failed address, with one of registers in the register group on a bit basis.
The method for compensating a failure in a semiconductor device with a memory, comprises the steps of: failure diagnostic step of diagnosing the memory to detect a failed address; and failed bit compensation step of compensating a failed bit in the memory which is specified by the failed address, based on the diagnostic result in failure diagnostic step.
According to the method of the present invention, the failure diagnostic device diagnoses the built-in memory to detect the address of the failed bit in the memory. The failed bit compensation device compensates the failed bit. Thus, the present invention performs the self-diagnostic process for the memory, and compensates the failed bit, eliminating failure compensation step from the manufacturing process. Because the failed bits specified by the failed address are individually compensated, the present invention can cope with various failures efficiently.
In the failure diagnostic step, the diagnosis of the memory is made within the address area for specified data to be stored in the memory. The address area in which data is not stored is excluded from the target of the diagnostic process, and the load of the failure diagnostic process can be decreased.
In the failure diagnostic step, the diagnosis of the memory is made using specified data to be stored in the memory.
Even when a failure exists, the failure is not detected as long as it does not hinder specified data from being stored. The target is limited to the minimum range in the memory required to store the specified data, thus minimizing the diagnostic process.
In the failure diagnostic step, the diagnosis of the memory is made outside the address area for specified data, which is to be stored in the memory, to detect a normal (defect-free) address. In the failed bit compensation step, the failed address is substituted for the normal address. Therefore, the efficiency in the use of the bits in the memory is improved.
The failed bit compensation step comprises the steps of: a) storing the failed address detected in failure diagnostic step; b) detecting the coincidence between the failed address and the address sent to the memory; and c) selecting one of the memory and the register group to a data bus when the coincidence between the failed address and the address sent to the memory is detected.
The address sent to the memory is compared with the failed address stored in the failed address storage device, and detects the coincidence. Based on this detection, one of the memory and the register group is selected and is connected to the data bus. When the failed address is accessed, the failed address is substituted for the register group, to thereby compensate the failure in the memory. The failed bit compensation device replaces the failed bit, specified by the failed address, with one of registers in the register group on a bit basis.